Microsemi

Keynotes

Keynote 1 – Toshiba Memory
Meeting Application Needs with a New Generation
of Advanced Storage Technology

Tuesday, August 6th, 11:00 am

Jeremy Werner

Jeremy Werner

Senior Vice President and General Manager, SSD Business Unit

Toshiba Memory

Jeremy Werner is senior vice president and general manager, SSD business unit, Toshiba Memory America, Inc., where he leads the team focused on defining, promoting, supporting and delivering solid state drives and Shared Accelerated Storage software that advance enterprise transformation, enable cloud infrastructure, and provide outstanding user experiences in PCs, embedded systems, automobiles, and consumer electronics. Jeremy has nearly 20 years of experience in the memory industry, he was previously VP Sales/Marketing at Tidal Systems, a developer of flash controllers acquired by Micron. He has also held marketing management positions at Seagate, LSI, and SandForce. He holds 23 patents in storage technology. He earned a BSEE at Cornell University.

Shigeo (Jeff) Ohshima, Technology Executive, SSD Application Engineering

Shigeo (Jeff) Ohshima

Technology Executive, SSD Application Engineering    

Toshiba Memory

Jeff Ohshima is a member of the technology executive team at Toshiba Memory, where he focuses on SSD development and applications engineering. He was previously VP Memory Technology Executive at Toshiba America Electronic Components focused on flash memory with an emphasis on SSDs. He has also been Senior Manager R&D in the advanced NAND flash memory design department, responsible for 70 nm, 56 nm, 43 nm, and 32 nm part design. He has worked on memory at Toshiba for over 30 years, including 20 years on DRAM where he acted as a lead design for application specific memories and did technical marketing. Ohshima has served as a Visiting Research Scientist at Stanford University. He holds a BSEE and MSEE from Tokyo’s Keio University.

Abstract:
The flash industry has recently produced game-changing innovations in density, latency, and form factors resulting in large cost-performance benefits. To address the wide spectrum of storage demands coming from phone/IoT devices, mobile compute, and data centers, new flash architectures are essential to handle next generation applications. Challenges have emerged in satisfying the demands of on-premise and cloud data centers while also addressing the data needs of consumers, mobile workforces, and organizations depending on high speed access to information assets. Future technology must include not only new architectures and more layers in flash chip designs, but also a roadmap for QLC flash and beyond, new classes of NVMe SSDs, and new software technologies. They must all come together to enable and accelerate the next wave of applications including real-time analytics, AI/ML, high-performance computing, IoT, and virtual and augmented reality.


Lifetime Achievement Awards

 Tuesday, August 6th, 11:30 am



To Be Announced



Keynote 2 – WDC
Data-centric Architecture
for the Zettabyte Age

Tuesday, August 6th, 11:40 am

WDC-Siva-Sivaram.jpg

Dr. Siva Sivaram

Siva Sivaram, Executive Vice President, Silicon Technology & Manufacturing

Western Digital

Dr. Siva Sivaram is Executive Vice President of Silicon Technology and Manufacturing for Western Digital, responsible for the company’s industry-leading NAND flash memories and other memory and storage technologies. Sivaram has more than 35 years of experience in semiconductor technology and manufacturing. He has held executive positions at Intel, Matrix Semiconductor and at SanDisk after its acquisition of Matrix. Additionally, he was the founder and CEO of Twin Creeks Technologies, a solar panel and equipment company. Sivaram serves on the board of directors of the Global Semiconductor Alliance and the US-India Business Council. He has been on the board member of several start-up firms and was entrepreneur-in-residence at Crosslink Capital and XSeed Capital. Sivaram received his doctorate and master’s degrees in materials science from the Rensselaer Polytechnic Institute where he has been elected to its Board of Trustees. Additionally, he is a Distinguished Alumnus of the National Institute of Technology, Tiruchi, India, where he received his bachelor’s degree in mechanical engineering. Sivaram has published numerous technical papers and a textbook on Chemical Vapor Deposition and holds several patents in semiconductor and solar technologies.

WDC-Christopher-Bergey

Christopher Bergey

Christopher Bergey, Senior Vice President, Devices

Western Digital

Christopher Bergey is Senior Vice President of Devices Product Marketing and Management at Western Digital responsible for the Data Center, Client Compute, Embedded and Mobility product offerings. Bergey leads Western Digital’s devices product portfolio, from definition and strategy to concept and customer acceptance. Previously, Bergey was Vice President for Embedded and Integrated Systems (EIS) at Western Digital, focused on developing and driving product strategies in mobile and compute, as well as new markets including automotive, connected home, smart city and industrial IoT market segments. In this role, he led industry adoption of TLC (three-bits-per-cell) into the mobile market. Prior to joining Western Digital in 2014, Bergey held multiple executive positions including VP of Marketing at Luxtera, VP of Mobile and Wireless at Broadcom, and Director of VLSI marketing at the Multilink Technology Corporation. Through this experience, Bergey has uniquely spent his career driving connectivity innovation in cloud datacenters as well as mobile and embedded markets. Bergey holds a Bachelor of Science degree in Electrical Engineering from Drexel University and a Master of Business Administration in Finance and Economics from the University of Maryland. He is a frequent author and speaker on topics such as IoT, mobility, and the implementation of data-centric memories and architectures to address the Zettabyte Age.

Abstract:
In order to meet the explosive growth of data, flash memory manufacturers must continue to advance technology. The introduction of the charge trap memory cell helped enable fast and high-endurance SLC, brought TLC into the mainstream and is now leading to the introduction of QLC. However, the real potential of QLC and other forms of high-density storage such as Shingled Magnetic Recording (SMR) hard disk drives is not realized in today’s data center. A new, data-centric architecture is needed to address the growing complexity of workloads, applications and AI/IoT datasets. It must involve multiple tiers of purpose-built compute and storage, as well as new approaches to system software. Zoned-block storage allows data to be intelligently placed and sequenced. This enables lower TCO and optimizes the use of emerging high-density storage, without sacrificing performance. In the Zettabyte Age, architects need to explore innovative approaches to data center architecture to unlock the benefits of the next generation of storage.

Tech Target

 Thursday, August 8th, 1:40pm



To Be Announced




Keynote 3: SK hynix
Subject:
To Be Announced

Tuesday, August 6th, 1:50 pm

hynix-Hongsok-Choi

Hongsok Choi

VP of NAND Development and Design

SK hynix

Stay Tuned!!! The speaker bio will be posted shortly. Keynote Addresses are the most popular attraction at Flash Memory Summit as you will hear from Senior Executives of the leading and emerging storage companies.

They will be an opportunity to keep a pulse on the fast-moving changes in storage hardware and software as IT data center workloads progress to address the next wave of exciting applications, such as Artificial Intelligence (AI), and Machine Learning (ML), and Augmented Reality/Virtual Reality (AR/VR).

Flash Memory Summit is the most prestigious conference on flash memory technology and is the place to hear from the storage industry leaders. Please come back soon to see the full list of Keynote Speakers!



Keynote 4: NGD
Subject:
To be Announced

Tuesday, August 6th, 2:20pm

NGD-Vladimir-Alves

Vladimir Alves

Co-Founder & CTO

NGD Systems

Vladimir Alves is co-founder/CTO at NGD Systems, where he focuses on developing SoCs that implement intelligent storage technology for data centers and fog computing. He has developed SoC-based solid state solutions for over 10 years, during which his teams have released many enterprise SSD controllers. Before co-founding NGD Systems, he was Sr Director of SSD SoC Development at Western Digital and STEC. He is the author of over 30 scientific publications on subjects including SoCs and computer architecture, and the co-author of over 20 patents. He earned his PhD in microelectronics from the National Polytechnic Institute of Grenoble, France.

Christopher Bergey, Executive Vice President of Devices

Scott Shadley

VP Marketing

NGD Systems

Scott Shadley is VP Marketing at NGD Systems where he leads marketing, product management, and product development for the company’s industry-leading computational storage. He has been a key figure in promoting computational storage, being co-chair of the SNIA Technical Working Group on the subject which he helped found, and speaking on the subject at Open Compute Summit, Flash Memory Summit, NVMe Developer Days, and many other events, press interviews, blogs, and webinars. Before joining NGD Systems, Scott managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were multimillion dollar sellers. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.


Keynote 5: IBM
Leveraging Flash Memory
for High Performance AI

Tuesday, August 6th, 3:00 pm

IBM-Steven-Eliuk

Steven Eliuk, Ph.D.

Vice President of Deep Learning, Global Chief Data Office

IBM

Steven Eliuk is Vice President Deep Learning, Global Chief Data Office (GCDO) at IBM, where he leads the development of platform and infrastructure components for machine learning and deep learning in the Cognitive Enterprise Data Platform, IBM’s data lake. He also is focused on applying DL in the enterprise to accelerate the use of cognition in internal processes while maintaining governance, security, privacy, and trust. His work has both generated revenue and showcased cognition at IBM scale to clients. Before joining IBM, Steven led the design of high performance computing (HPC) infrastructure for artificial intelligence and launched the first model parallel distributed training framework for HPC at Samsung Research America. Steven earned a PhD in Computer Science from the University of Alberta. He has presented at many events, including IBM Think, IBM CDO Summit, Nvidia GPU Developers Conference, IEEE, and more.

Abstract:
Improving the use of data is a top priority of business organizations around the world. A key aspect is to develop an enterprise information architecture that provides an effective AI solution. Data must be accessible, trusted, and ready to be analyzed by AI algorithms. Data of every type, regardless of where it lives, needs to be part of the AI journey. We must provide an AI-friendly infrastructure that includes hybrid cloud, multi-cloud, virtualized, and containerized environments. Machine learning can then be applied to the results for a competitive advantage.

Data management challenges ensue with the ingestion, aggregation, and siloing of data. The problems are compounded by multiple copies and potentially stale data that can detract from the AI environment. Architectural challenges can affect security, protection, and global accessibility to data assets.

The challenges can be met by classifying and preparing data sets, implementing AI data workflows. and deploying AI models capable of meeting service level objectives. See how real world customers are executing AI transformation and applying best practices to successfully leveraging flash memory for AI performance optimization and employing innovative techniques to increase business value.


Keynote 6: Intel
Breakthrough Data-Centric Computing
with a New Memory Tier

Wednesday, August 7th, 11:00 am

Intel-Alper-Ilkabahar

Alper Ilkabahar

Vice President & General Manager

Intel

Alper Ilkbahar is General Manager of Data Center Memory and Storage Solutions and Vice President Data Center Group at Intel, where he led the introduction of the world’s first persistent memory to market in 2018. Before taking on this position, he oversaw the commercialization of new non-volatile, high-performance memory technology at Matrix Semiconductor and SanDisk, as well as holding design engineering and management roles in Intel’s microprocessor division. A 27-year veteran of the semiconductor industry, he earned an MSEE from the University of Michigan and an MBA from the Wharton School University of Pennsylvania. He holds over 50 patents in semiconductor process, device design, and testing and has published multiple conference and journal papers.

Abstract:
New and increasingly important data-centric workloads, such as real-time analytics, AI/ML, VR/AR, IoT, HPC, and cybersecurity, demand tremendous throughput at a reasonable price. The current memory/storage hierarchy of DRAM and flash cannot do the job alone. A new tier is needed that is persistent, high-throughput/low-latency, production-proven, low-cost, scalable, and simple to integrate into existing designs. Such a tier can provide a tremendous speed boost at an affordable cost. Use cases are already available for a wide variety of key applications, and results show major advances in speed, cost/performance ratio, power consumption, and scalability.


Keynote 7: Microchip
Subject:
To Be Announced

Wednesday, August 7th, 11:30 pm

Microchip-Andrew-Dieckmann

Andrew Dieckmann

VP of Marketing for Data Center Solutions

Microchip

Andrew Dieckmann is VP of Marketing and Applications Engineering for Data Center Solutions Division at Microsemi, a wholly owned subsidiary of Microchip Technology. He is responsible for product management, product marketing, product strategy and the application engineering teams supporting Microsemi’s broad portfolio of storage solutions including SSD controllers, RAID solutions, HBAs, PCIe switches and SAS expanders. Prior to Microsemi, Andrew was a long-time member of PMC-Sierra’s Enterprise Storage Division where he helped build the business from inception to become the largest division at the company at PMC-Sierra when it was acquired by Microsemi. Andrew earned a BSEE degree from Lakehead University in Ontario, Canada.


Keynote 8: Mellanox
Feeding Data Hungry GPUs with Networked Flash

Wednesday, August 7th, 1:00pm

Mellanox-Chris-Lamb

Chris Lamb

VP Computer Software at NVIDIA

Mellanox

Chris leads software engineering for the CUDA platform, DGX systems, data-center distributed systems such as Kubernetes, and NGC, a registry for accelerated solutions on NVIDIA platforms; software that spans supercomputers, clouds, workstations, robots, and self-driving cars. Over his career he's worked in diverse areas from many-core computer architecture, compiler and performance tools engineering, embedded systems, microwave communication, networking, and distributed systems. Chris has a BS in Computer Engineering from the University of Illinois at Urbana-Champaign.

Mallanox-Micheal-Kegan

Michael Kegan

VP Compute Software 

Mellanox

Michael Kagan is a co-founder and CTO of Mellanox Technologies where he focuses on using high-speed networking to improve application performance. He works on problems in high-performance computing, cloud computing, and megawebsites. He has been a leader in establishing new standards for high-speed networking, with a particular emphasis on RDMA over Converged Ethernet (RoCE) and the Infiniband technology. Before joining Mellanox, Mr. Kagan worked at Intel where he managed the Pentium MMX design and the PC product group. He holds a BSEE from the Technion — Israel Institute of Technology.

Abstract:
Today GPUs (Graphics Processing Units), are driving the mathematically intensive artificial intelligence (AI) and machine learning (ML) applications which have the promise of revolutionizing almost every aspect of our world. They are also data hungry and fast, which means they can consume terabytes of data very quickly. Often more data than can be stored locally. By interfacing GPUs to ultra high performance InfiniBand and Ethernet storage networks you solve the local storage capacity limitation. Especially when the networked storage in flashed based. Join the leaders, Nvidia and Mellanox, in GPUs and High Performance Networking, to understand how these two amazing technologies can be combined to turbocharge the AI and ML revolution.


Keynote 9: ScaleFlux
Subject:
To Be Announced

Wednesday, August 7th, 1:30 pm

ScaleFlux-Dr-Hao-Zhong

Dr. Hao Zhong

Co-Founder & CEO

ScaleFlux

Dr. Hao Zhong is CEO & Co-Founder, ScaleFlux Inc., a developer of high-performance flash controllers and appliances. He is a passionate technology innovator and entrepreneur who has developed many cutting-edge technologies and products in the data storage and computing industries. He currently focuses on delivering Computational Storage to the worldwide market.

Before co-founding ScaleFlux, Hao was a Senior Director at Fusion-io where he led the flash memory technology team and enabled LDPC in industry-leading PCIe SSDs. He has also been an engineering director at SandForce working on SSD controller chips and an architect at LSI, where he was the key contributor to the industry leading LDPC read channel chip in 2008. Hao earned a PhD in Electrical Engineering from Rensselaer Polytechnic Institute (New York). He holds over 80 storage patents.


Keynote 10: Marvell
Subject:
To Be Announced

Wednesday, August 7th, 2:10 pm

Marvell-Nigel-Alvares

Nigel Alvares

VP SSD and Data Center Storage Solutions

Marvell

Nigel Alvares is VP SSD and Data Center Storage Solutions at Marvell Semiconductor, where he is responsible for SSD controllers and data center storage chipsets. Under his leadership, Marvell is driving new solutions to address the needs of virtualized, multi-tenant cloud data centers, edge computing infrastructures, and client devices. Before joining Marvell, Nigel worked for Inphi, a maker of high-performance memories where he helped launch innovative non-volatile memory chipsets for the popular NVDIMMs. Prior to Inphi, Nigel was a founding member of PMC-Sierra’s Enterprise Storage Division and helped build it into the company’s largest business with its widely deployed controller and disk interconnect products. He has over 20 years of experience in data storage and networking. He earned a BSEE from McGill University (Montreal, Canada) and an MBA from Simon Fraser University (Vancouver, Canada).


Keynote 11: Xilinx
FPGAs:
The Key to Accelerating High-Speed Storage Systems

Wednesday, August 7th, 2:40 pm

Xilinx-Salil-Raje

Salil Raje

Executive Vice President and General Manager, Data Center Group

Xilinx

XilinxSalil Raje heads the Data Center Group (DCG) for Xilinx, leading a global team of engineering, sales, and marketing professionals dedicated to the data center, the fastest growing market for FPGAs. His group helps top hyperscalers and enterprise cloud providers harness intelligent, adaptable infrastructure to improve performance, power efficiency, and operating costs. He has previously led initiatives in development environments, contributed greatly to expansion efforts in machine learning and vision applications, and improved FPGA design tools. He has over 20-years of experience in the technology industry, holds eight patents in electronic design tools, ASIC, and FPGA designs, and has written more than 15 industry-recognized research papers. He earned a PhD in computer science from Northwestern University.

Abstract:
With the advent of flash storage and persistent memory, storage is no longer a roadblock to better system performance. Data can already be transferred from SSDs at thousands of times the speed of hard drives. Now NVMe and new technologies such as 3D XPoint are putting further pressure on other system resources with ever-higher data rates. How can processors and networks keep up? With traditional system design – they can’t. Heterogenous architectures and computational storage are becoming the answer to this challenge, with FPGAs leading the charge. This long-proven technology can offload protocol overhead, accelerate storage services such as compression and security, and perform local processing for computational storage. FPGAs are fast, flexible, and capable of handling a wide variety of algorithms and procedures. They can meet today’s challenges and support tomorrow’s emerging applications such as AI/ML, real-time analytics, video and image processing, cybersecurity, and 5G wireless.


Keynote 12: FADU
Delivering the Breakthrough Flash Storage Architecture
Needed for Next Generation Computing

Thursday, August 8th, 11:00 am

FADU-Jihyo-Lee

Jihyo Lee

Co-Founder & CEO

FADU

Jihyo Lee is the co-founder and CEO of FADU Technology. Jihyo is a former partner at Bain & Capital and a successful serial entrepreneur involved in multiple businesses in technology, telecom and energy. He successfully led and initiated Bain & Capital’s technology sector focus, including semiconductor and display panel components, devices (mobile and TV) and services (cloud and internet/contents). Jihyo has been a C-level advisor to global technology companies, leading projects to solve key strategic issues. As CEO of FADU, he has established FADU as a fabless semiconductor innovator, uniting exceptional industry talent to create a revolution in data center and storage for next generation computing architectures.

Abstract:
End use applications such as virtual reality, autonomous driving, video streaming and the explosion of real-time connected devices has put tremendous storage performance demands on hyperscale and enterprise data centers. These data centers, more than ever, need to scale up storage capacity and performance while meeting constraints on power consumption. The issue they face is a storage architecture tied to inefficient legacy standards. The answer is to develop a new solution, optimized solely on Flash technology that unshackles the performance of the Flash controller, Flash memory and storage software. A new generation of Flash-based storage solutions will support the demands of the industry and lift the Flash supplier base out of stagnation by relieving them from ties to the past.

About FADU:
FADU is a fabless semiconductor company focusing on advanced Flash-based memory storage solutions and systems for next generation computing. FADU is answering the industry’s call to enable future end applications that are computation and storage intensive. The innovative Flash solution designs are independent of legacy storage architectures and include the Annapurna PCIe 3.0 X 4 NVMe SSD controller and Bravo M.2 and Dual U.2 Enterprise SSDs. FADU is setting the benchmark for a low power, high performance and feature rich future.

Super Women in Flash

 Thursday, August 8th, 11:30 am



To Be Announced




Keynote 13: InnoGrit
How to get 2x Throughput and IOPs
by System and Controller Optimization

Thursday, August 8th, 11:40am

InnoGrit-Zining-Wu

Zining Wu

Founder & CEO

InnoGrit

Dr. Zining Wu is the co-founder and CEO of Innogrit Corporation, a fabless semiconductor startup focusing on data storage, management, and processing.

Before founding Innogrit in October 2016, Dr. Zining Wu worked at Marvell for 17 years, where he last served as Chief Technology Officer of Marvell Technology Group. In this role, he was responsible for overseeing all technical aspects of the company, including establishing the company's technical vision, directing strategic initiatives for future growth, and managing central engineering for R&D execution. Prior to his CTO role, Dr. Wu was the Vice President of Data Storage Technologies at Marvell, where he was responsible for innovative storage technologies for the hard disk drive and SSD controllers.

Dr. Wu holds a Bachelor of Science degree in Electronic Engineering from Tsinghua University in Beijing, China, and a Master of Science Degree and Ph.D. in Electrical Engineering from Stanford University.

Abstract:
As the SSD industry migrates from PCIe Gen3 to Gen4 and even to Gen5, can users really enjoy the doubling of throughput and IOPs? In this presentation, we analyze system-level bottlenecks and discuss how to address them. For PC users, we show that PCIe Gen4 combined with host managed FTL can greatly boost system performance and reduce power. For data centers, tiered storage with fast NAND and hardware offload engines can help unleash the true potential of PCIe Gen4 and produce a high-performance storage system for demanding data center applications.




NETINT
Conference ConCepts